Power Vs VDD in Sub-threshold Digital Logic By

1. Power Vs VDD in Sub-threshold Digital LogicBy Kinchit Desai Under the Guidance of Dr. Carl Sechen NDL(Nanometer Design Lab) University of Texas at Dallas

2. Executive Summary • This document is for background purposes only. A specific value for a minimum nominal process specification is not calculated. • At sub-threshold VDD values, reduced circuit swing at the input of gates causes exponentially increasing circuit delay and static leakage (Idsub) as VDD decreases. Dynamic energy consumption continues to drop with reduction in both V2 and F terms (in P=C V2 F) as VDD decreases. The VDD value where the exponentially increasing static leakage energy curve intersects with the dynamic energy reduction curve forms the minimum energy voltage. The minimum energy VDD is always higher than the absolute minimum VDD at which circuits operate correctly. • A recommendation for setting the nominal minimum process supply voltage can be computed as follows o Min VDD = Vth + 5 * sigma(VDD) + Body Effect + Static Noise Margin + appropriate additional margin. • Sigma VDD needs to include a VDD dependence and a dependence on transistors width and length. • The phenomenon described above only occurs to circuits and not to individual transistors.

3. Scope of the Problem • At sub-threshold VDD's, the exponential relationship between VDD, randomly varying Vth and cell delay will cause problems with industry • standard timing closure flows and tools that assume a linear and predicable • relationship between VDD and delay. • This is of greatest concern with respect to hold margin on fast paths, but it will also cause unpredictable yield fallout with respect to operating frequencies. There is also an exponential dependence of delay on temperature that will cause problems at probe and final test • Avoidance of this region of operation seems simple in theory. • Vth variation is a strong function of Random Dopant Fluctuation and has a normal probability distribution. In 65nm, Vth and Ids variation is also a function of VDD and transistor L. For nominal L values, Ids variation increases with decreasing voltage while Vth variation does not change much. • For larger L values, Vth variation and Ids both increase with decreasing VDD.

4. What is sub threshold current In a sub-threshold CMOS inverter: • Both transistors are conducting continuously. • The drain to source resistances of the NMOS and PMOS transistors form a voltage dependent resistive voltage divider. • The Vout of the resistive voltage divider (the output voltage of the inverter) is set by the inverter VIN bias voltage. • VOH is always < VDD and VOL is always > VSS. • There is zero static noise margin in this region of operation and as such VIL and VIH are not well defined. The output voltage will respond to any change in input voltage. • At sub-threshold VDD values: • Both on and off currents are exponentially dependent on VDD, but off-current is not reduced as rapidly as on-current as a function of reductions in VDD. • The Ion/Ioff ratio decreases steadily with decreasing sub-thresholdVDD, causing the circuit output voltage swing to be reduced as a percentage of VDD.

5. Sub threshold operation

6. Minimum energy Voltage-Vmin

7. Design for Sub Vt Energy Efficiency • Maximize Utility of transistors Avoid idle transistors that only contribute leakage. • Simple architecture Avoid complex logic even if infrequently used. • Increase pipeline depth ,but: avoid leakage of additional by-pass logic. • Maximize Code density Leakage in memory system quick dominates total energy. • Architecture must be constructed with Sub-Vt in mind.

8. Ongoing Work • Miminum Vdd point for 130nm process has been found and currently working to find the point for 45nm • Circuits like different processor are now been trested for the minimum vdd point • DRAM tried to be operated on the same Vdd point