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EE365 Adv. Digital Circuit Design Clarkson University Lecture #7 Intro to MSI PLDs and Decoders

EE365 Adv. Digital Circuit Design Clarkson University Lecture #7 Intro to MSI PLDs and Decoders. Topics. MSI Intro PLDs Decoders. Lect #7. Rissacher EE365. Role of MSI Components in Logic Design. Gates are the fundamental building blocks of logic - the “atoms”.

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EE365 Adv. Digital Circuit Design Clarkson University Lecture #7 Intro to MSI PLDs and Decoders

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  1. EE365 Adv. Digital Circuit Design Clarkson University Lecture #7 Intro to MSI PLDs and Decoders

  2. Topics • MSI Intro • PLDs • Decoders Lect #7 Rissacher EE365

  3. Role of MSI Components in Logic Design • Gates are the fundamental building blocks of logic - the “atoms”. • Medium Scale Integrated (MSI) components are the “molecules” - the commonly occurring functions. • MSI components form the building blocks for much more complex functions . Lect #7 Rissacher EE365

  4. MSI vs. Gate Level Design • Functions more complex - more inputs and/or outputs. • Find a good, feasible design, not necessarily optimal. • Not restricted to two-level logic. • Trade-off propagation delay with simplicity of design. • Keep IC count low (usually ignore gate count). Lect #7 Rissacher EE365

  5. MSI vs. Gate Level Design • Look for designs which are scalable - easily expanded to handle more inputs. • Look for designs which are hierarchical - built upon already designed functions. • No automated, general design algorithm - must be creative. • Same principles apply to custom VLSI or ASIC design. Lect #7 Rissacher EE365

  6. Programmable Logic Arrays (PLAs) • Any combinational logic function can be realized as a sum of products. • Idea: Build a large AND-OR array with lots of inputs and product terms, and programmable connections. • n inputs • AND gates have 2n inputs -- true and complement of each variable. • m outputs, driven by large OR gates • Each AND gate is programmably connected to each output’s OR gate. • p AND gates (p<<2n) Lect #7 Rissacher EE365

  7. Example: 4x3 PLA, 6 product terms Lect #7 Rissacher EE365

  8. Compact representation • Actually, closer to physical layout (“wired logic”). Lect #7 Rissacher EE365

  9. Some product terms Lect #7 Rissacher EE365

  10. PLA Electrical Design • See Section 5.3.5 -- wired-AND logic Lect #7 Rissacher EE365

  11. Programmable Array Logic (PALs) • How beneficial is product sharing? • Not enough to justify the extra AND array • PALs ==> fixed OR array • Each AND gate is permanently connected to a certain OR gate. • Example: PAL16L8 Lect #7 Rissacher EE365

  12. 10 primary inputs • 8 outputs, with 7 ANDs per output • 1 AND for 3-state enable • 6 outputs available as inputs • more inputs, at expense of outputs • two-pass logic, helper terms • Note inversion on outputs • output is complement of sum-of-products • newer PALs have selectable inversion Lect #7 Rissacher EE365

  13. Designing with PALs • Compare number of inputs and outputs of the problem with available resources in the PAL. • Write equations for each output using ABEL. • Compile the ABEL program, determine whether minimimized equations fit in the available AND terms. • If no fit, try modifying equations or providing “helper” terms. Lect #7 Rissacher EE365

  14. Decoders • General decoder structure • Typically n inputs, 2n outputs • 2-to-4, 3-to-8, 4-to-16, etc. Lect #7 Rissacher EE365

  15. Note “x” (don’t care) notation. Binary 2-to-4 decoder Lect #7 Rissacher EE365

  16. 2-to-4-decoder logic diagram Lect #7 Rissacher EE365

  17. MSI 2-to-4 decoder • Input buffering (less load) • NAND gates (faster) Lect #7 Rissacher EE365

  18. Decoder Symbol Lect #7 Rissacher EE365

  19. Complete 74x139 Decoder Lect #7 Rissacher EE365

  20. More decoder symbols Lect #7 Rissacher EE365

  21. Minterms & Decoders Note that outputs to decoders correspond to Minterms Lect #7 Rissacher EE365

  22. Minterms & Decoders • SOP can be formed by combining outputs • i.e., Z = (I0’ • I1’) + (I0 • I1’) • Most Decoders have active-low outputs, so they need to be inverted or a NAND can be substituted Lect #7 Rissacher EE365

  23. 3-to-8 decoder Lect #7 Rissacher EE365

  24. 74x138 3-to-8-decoder symbol Lect #7 Rissacher EE365

  25. Decoder cascading 4-to-16 decoder Lect #7 Rissacher EE365

  26. In-Class Practice Problem • Wire the 74x139 to make a 3-to-8 decoder • You may use inverters Lect #7 Rissacher EE365

  27. In-Class Practice Problem • Note that this would not normally be done since the 74x138 does the same thing A B C Lect #7 Rissacher EE365

  28. More cascading 5-to-32 decoder Lect #7 Rissacher EE365

  29. Decoder applications • Microprocessor memory systems • selecting different banks of memory • Microprocessor input/output systems • selecting different devices • Microprocessor instruction decoding • enabling different functional units • Memory chips • enabling different rows of memory depending on address • Lots of other applications Lect #7 Rissacher EE365

  30. Next time • Buffers • Drivers • Encoders • Multiplexers • Exclusive OR Gates Lect #7 Rissacher EE365

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