EE365 Adv. Digital Circuit Design Clarkson University Lecture #1 Course Outline Number Systems

1. EE365 Adv. Digital Circuit Design Clarkson University Lecture #1 Course Outline Number Systems

2. Syllabus • No mid-course exams (only final exam) • Design Problems heavily weighted • Optional homeworks • Quizzes (every few days) correspond to HWs • Textbook: does everyone have it? • Office Hours: where/when • Contact information (phone, e-mail, AIM) Lect #1 Rissacher EE365

3. Course Website • www.clarkson.edu/class/ee365 • Schedule • Notes (suggest printing before class) • Handouts • Class Location (some will be in computer lab) • Links Lect #1 Rissacher EE365

4. Lecture Structure • Interrupt me at anytime for questions • Discussions encouraged • Grade not based on attendance • Feel free to excuse yourself at any time (e.g., if you’re falling asleep go stretch your legs and buy a mountain dew, or leave after quiz is over) • Bring scrap paper: I may give in-class practice problems Lect #1 Rissacher EE365

5. Projects • Heavily weighted • May take some time, start early & use the weekends • Will have at least one in-class help session for each project. • Each project will require you to hand in files on floppy or CD (your choice)… make sure you have a supply before the first project is due Lect #1 Rissacher EE365

6. Overview • General Topics: • Basic Logic Review • Logic Laws/Theorems/Methods • VHDL • Transistor-Level Logic Implementation • Electrical Behavior (timing, hazards, etc.) • MSI Devices (Gates, Encoders, MUXs, registers, etc.) • Sequential Logic • LSI/VLSI Devices (memory, CPLDs, FPGAs) Lect #1 Rissacher EE365

7. Number Systems & Math Will be covered later today Lect #1 Rissacher EE365

8. Logic Laws & Methods • DeMorgan’s Law, Sum of Products, Product of Sums • Minterm, Maxterm • Karnaugh Maps • Commutativity, Associativity, etc. Lect #1 Rissacher EE365

9. VHDL entity and2 isport ( a, b : in bit; y : out bit );end and2; architecture basic of and2 isbegin and2_behavior : processbegin y <= a and b after 2 ns;wait on a, b;end process and2_behavior; end basic; Lect #1 Rissacher EE365

10. Transistor-Level Logic Implementation Lect #1 Rissacher EE365

11. Electrical Behavior • Propagation Delay • Fan-In, Fan-Out • Timing Hazards • etc Lect #1 Rissacher EE365

12. MSI Devices Encoders, Decoders, Multiplexers, Registers, PLDs, Comparators, Adders, Subtractors, ALUs, etc. Lect #1 Rissacher EE365

13. Sequential Logic Lect #1 Rissacher EE365

14. LSI/VLSI Devices • ROMs • SRAM • DRAM • CPLDs • FPGAs Lect #1 Rissacher EE365

15. Number Systems • Binary • Hex • Octal • Addition/Subtraction • Negative Numbers Lect #1 Rissacher EE365

16. Number Systems 2n 10n 8n 16n Where n is the bit #, or decimal place Lect #1 Rissacher EE365

17. Binary Addition Lect #1 Rissacher EE365

18. Binary Subtraction Lect #1 Rissacher EE365

19. Negative Binary Numbers • Signed-Magnitude • Two’s Complement Lect #1 Rissacher EE365

20. Signed-Magnitude • MSB represents the sign • Other bits represent the value • 01010101 = +85 • 11010101 = -85 Lect #1 Rissacher EE365

21. Two’s Complement • MSB represents the sign • Other bits represent the value if positive • Complement + 1 of other bits represents the value if negative • creates a continuous number line so that if we start with most negative number and count up, we see that each successive number can be obtained • e.g., 17 = 00010001, complement = 11101110 + 1 = 11101111 = -17 Lect #1 Rissacher EE365

22. Two’s Complement Addition/Subtraction +3 0011 + +40100 +7 0111 +4 0100 + -71001 -3 1101 • Ignore carry bits into MSB • For subtraction, simply negate one of the numbers Lect #1 Rissacher EE365

23. Binary Multiplication/Division • Very similar to the multiplication and long division methods that we learned in elementary school Lect #1 Rissacher EE365

24. Binary Multiplication • Multiplication is achieved by adding a list of shifted multiplicands according to the digits of the multiplier • Un-signed example: Lect #1 Rissacher EE365

25. Binary Multiplication • Instead of listing all shifted multiplicands before adding, we can add each shifted multiplicand to a partial product (move convenient in a digital system): Lect #1 Rissacher EE365

26. Two’s Complement Multiplication • A sequence of two’s-complement additions is similar except for the last step where the shifted multiplicand (corresponding to the MSB) must be negated: Lect #1 Rissacher EE365

27. Binary Division • Use long division, shift and subtract (shown below) • Direct two’s complement method not discussed here, but sign can be handled by negating the quotient if the dividend and divisor had different signs Lect #1 Rissacher EE365

28. Next Time • Logic Theorems • Sum-of-Products vs. Product-of-Sums • Minterms/Maxterms • Logic Function Representations Lect #1 Rissacher EE365

29. Homework • E-mail me your contact information and preferred methods of reaching you • Please include e-mail, phone, messenger names, etc. • my address: rissacdj@clarkson.edu Lect #1 Rissacher EE365