Performed by: Yahel Ben-Avraham Yaron Rimmer Instructor: Mony Orbach

1. Technion - Israel institute of technology department of Electrical Engineering הטכניון - מכון טכנולוגי לישראלהפקולטה להנדסת חשמל High speed digital systems laboratory המעבדה למערכות ספרתיות מהירות סיכום פרויקט Subject: RISC processor implementation using Bluespec Performed by: Yahel Ben-Avraham Yaron Rimmer Instructor: Mony Orbach Spring 2013 1

2. High speed digital systems laboratory המעבדה למערכות ספרתיות מהירות Abstract Bluespec SystemVerilog (BSV) is a relatively new hardware description language (HDL), which characterizes in being a low-level HDL similar to SystemVerilog or VHDL, yet higher-level language. In this project we explore the advantages of BSV in implementing a piplined MIPS processor in a higher-level HDL, whilst letting the bluespec compiler make the optimizations. 2

3. High speed digital systems laboratory המעבדה למערכות ספרתיות מהירות System description Similarly to the basic 5-stage pipeline MIPS, the main pipeline consists of five logical stages: Fetch, Decode, Execute, Memory (which is divided to Memory1 and Memory2 for technical reasons) and Writeback. Each stage of the pipeline is implemented within a designated rule, which receives its required data in a struct from the previous stage of the pipeline by dequeuing the FIFO separating between the stages. After the rule finishes its work, the result data struct is enqueued into the next FIFO and so on. Global registers are used as a forwarding unit. 3

4. High speed digital systems laboratory המעבדה למערכות ספרתיות מהירות Specification • Implement a Pipelined MIPS processor using Bluespec System Verilog • Branch predictor and flushing unit • Hazard detection and forwarding unit • Run the design on FPGA 4

5. High speed digital systems laboratory המעבדה למערכות ספרתיות מהירות System Block Diagram 5

6. High speed digital systems laboratory המעבדה למערכות ספרתיות מהירות FPGA Block Diagram 6