Performed by: Yaakov Levenzon Ido Kahan Instructor: Mr. Mony Orbach

1. Technion - Israel Institute Of Technology department of Electrical Engineering הטכניון - מכון טכנולוגי לישראלהפקולטה להנדסת חשמל דו”ח סיכום פרויקט Subject: FPGA Encryption/Decryption Verification System Performed by: Yaakov Levenzon IdoKahan Instructor: Mr. Mony Orbach Spring Semester 2012 1

2. OurVerification System High speed digital systems laboratory המעבדה למערכות ספרתיות מהירות In our project we were asked to build an architecture on DE2 board, that will serve as a development and verification system to a hardware based encryption/decryption system.These encryption/decryption systems will be used on a USB flash drive (Disk On Key™). They are vital because unencrypted precious data on USB drives can be easily read by unwanted people. A team working on such systems can implement it into our verification system, and by a USB connection to a HOST PC, will be able to encrypt/decrypt files, thus checking their encryption/decryption system.Quality verification is that small factor which makes the difference between very good products and excellent products in the market.This is especially important when dealing with sensitive data, because it must be 100% safe. In order to ensure it, the encryption system must pass the utmost strict standards. This is when our verification system comes handy. 2

3. System description High speed digital systems laboratory המעבדה למערכות ספרתיות מהירות DE2 FPGA controller Nios II Host PC DLP AVALON USB Encryption /Decryption Out_Data FIFO 128->16 In_Data FIFO 8->128 3

4. Specification High speed digital systems laboratory המעבדה למערכות ספרתיות מהירות • Hardware : FPGA Cyclon II, on Altera DE2 Board. • DLP-USB245M • Throughput: 116 MHz (according to Quartus Compilation) • Latency: 16 + 1 + 1 = 18 clocks • 16 – to receive 128 bit from the DLP • 1 – our encryption system (NOT logic gate) • 1 – the FIFO before sending the data to the PC 4

5. System Block Diagram High speed digital systems laboratory המעבדה למערכות ספרתיות מהירות FPGA DLP PC FIFO Sending words Words by USB protocol Words on AVALON bus Unencrypted words PC PC Nios Nios FPGA DLP PC FIFO Encrypt/decrypt Words on AVALON bus Words by USB protocol Saving words Nios Nios PC PC Encrypting words Encrypted words 5

6. FPGA Block Diagram – Top Level High speed digital systems laboratory המעבדה למערכות ספרתיות מהירות Nios Encrypt_sys Fifo_out FSM Fifo_in controller 6

7. Technion - Israel Institute Of Technology department of Electrical Engineering הטכניון - מכון טכנולוגי לישראלהפקולטה להנדסת חשמל FPGA Encryption/Decryption System based on the Enigma Performed by: Yaakov Levenzon IdoKahan Instructor: Mr. Mony Orbach Spring Semester 2013 1

8. OurEnigma System High speed digital systems laboratory המעבדה למערכות ספרתיות מהירות In the 2nd section of the project, we changed our role, and became the designers and developers of the encryption\decryption system. Consulting with our advisor, we decided to design and implement the Enigma machine – the same machine which was used to deliver encrypted messages during the 2nd world war, which played a very important tool during the war.Of course, the development process were implemented and tested by using the verification system from our 1st section, and by creating a golden model, to test our algorithms. Designing and implementing on FPGA platform, and the increasing computing power since the 2nd world war, enabled us to add various improvements over the original Enigma machine, which contributed to a stronger encryption by using more characters – the entire ASCII table, bigger etc. 2

9. System description High speed digital systems laboratory המעבדה למערכות ספרתיות מהירות DE2 FPGA controller Nios II Host PC DLP AVALON USB ENIGMAEncryption /Decryption Out_Data FIFO 128->16 In_Data FIFO 8->128 3

10. Specification of the Enigma Design High speed digital systems laboratory המעבדה למערכות ספרתיות מהירות • Hardware : FPGA Cyclon II, on Altera DE2 Board. • DLP-USB245M • Throughput: 120 MHz (by QuartusCompilation) • Latency: 11 + 1 + 1 = 13 clocks • 11 – going through the pipes of the rotors • 1 – reg in clock • 1 – reg out clock 4

11. System Block Diagram – Encryption/Decryption High speed digital systems laboratory המעבדה למערכות ספרתיות מהירות From project A FIFO-IN Rotor 1-A Rotor 2-A Rotor 3-A Rotor 4-A Rotor 5-A unencrypted Different key Reflector Rotor 1-B Rotor 2-B Rotor 3-B Rotor 4-B Rotor 5-B From project A FIFO-OUT encrypted 5

12. FPGA Block Diagram – Top Level High speed digital systems laboratory המעבדה למערכות ספרתיות מהירות The Enigma 6

13. FPGA Block Diagram – Enigma Top Level High speed digital systems laboratory המעבדה למערכות ספרתיות מהירות Reflector Control first rotor The rotor before the reflector The rotor after the reflector Mux 2->1 Last rotor 7