Rich Katz, Grunt Engineer NASA Office of Logic Design

1. DRAFT Technical Test Planfor RTAX-S FPGAsby the NASA Office of Logic Design NOTIONAL PLAN and NUMBERS Rich Katz, Grunt Engineer NASA Office of Logic Design

2. Introductory Notes to Readers • In November 2005 a meeting was held to discuss a technical test plan for RTAX-S FPGAs with a broad audience of engineers both inside and external to NASA. Based on the meeting and follow up discussions, small changes (shown in blue) were made and the plan was enhanced. • Further comments and suggestions are being solicited and it is requested that they be sent to richard.bkatz@nasa.gov as soon as practical.

3. Objectives, Plan Overview, and Themes • “Get ahead of the curve” – find RTAX-S problems as early as possible and solve them • Commercial production in 2003, same feature size and foundry • Look for “known unknowns” such as programmed antifuse reliability. • Look for “unknown unknowns.” • Proceed similar to successful NASA Office of Logic Design independent test for NESC on RT54SX-S/RTSX-SU1 • Thorough and rigorous testing and analysis • Principle Investigator mode (rk, NASA OLD) • Diversity: Lot, device type, pattern, test protocol and methods 1http://klabs.org/richcontent/Reliability/actel/nasa_test/

4. Reliability Testing Overview • Complement the work of vendor (Actel) • RTAX-S Part quantities (~556) • Plus 182 AX series devices • Part types (all three models, focus on RTAX250S and RTAX2000S) • Test two lots • Independent of qualification lots already tested

5. Reliability Testing Protocols • Phase 0 (precedes and then overlaps with Phase 1) • D: Voltage Stress Test • S: Commercial Parts Test • Phase 1: Test patterns, part count split roughly 50-50 • A: One pattern to focus on antifuse • B: KTT (K-Labs Torture Test) replacing QBI for representative aggressive user (flight-like) pattern. Option to include additional antifuse tests as warranted. • Pipeline programming and testing to mitigate against testing risks and unexpected results • Temperatures: • Both HTOL (+125 C) and LTOL (-55 C) • Test thorough and conservative, independent of analytical models • Voltage: Increase stress as test proceeds, determine margin and critical internal FPGA structure.

6. Phase 0D: Voltage Stress Test • Experiment design: Increase voltage stress • Induce and identify failures. • Determine acceleration factor. • Determine V2 and V3 voltages for Phase 1 large population tests • Determine S1, S2, and S3 voltages for Phase 0S commercial test. • 4 sets of parts: • AX250: 16 RTAX250S: 16 • AX2000: 16 RTAX2000S: 16 • Test protocol: • Room temperature • EAQ Pattern • Increase voltage in steps: VCCA = {1.5, 1.6, D3, D4, D5, ….} • 48 hours at each voltage step • ATE at conclusion of each step • In situ, real-time current monitoring for anomalies • Provided by NASA OLD STUPID6 software already installed in Actel chambers

7. Phase 0S: Commercial Parts Test • Experiment: General Technology Stability • Induce and identify failures. • Determine acceleration factor. • Inexpensive basic test for early results • RTAX-S Long-term test is option for Phase 2. • Parts and Pattern: • Phase 0S-1: 150 AX250/PQ208 • Footprint compatible with RTAX250S/CQ208 • Phase 0S-2: TBD AX2000 • Pattern: KTT • Test protocol: • Room temperature • Lot splits with three voltages, S1, S2, and S3 • In situ, real-time monitoring for anomalies • External functional failure monitoring • On-chip timing measurement for antifuse faults

8. Phase 1A: Reliability Test: Antifuse Pattern • Extend and enhance Enhanced Lot Acceptance (ELA) testing: (E3LA) • Parts from two lots (276 total) • RTAX250S: 100 * 2 = 200 • RTAX1000S: 24 * 2 = 48 • RTAX2000S: 14 * 2 = 28 • Test protocol: • Two temperatures: -55 C (LTOL) and +125 C (HTOL) • Three increasing voltage steps: VCCA = {1.6, V2, V3} • 1000 hours at each voltage step • 500 hours HTOL • 500 hours LTOL Notes: Nominal voltage = 1.5V Max voltage = 1.575V

9. Phase 1B: Reliability Test: User Pattern • Parts from two lots (248 total) • QCMON Pattern (16 total) • RTAX250S: 8 * 2 = 16 • RTAX1000S: 0 • RTAX2000S: 0 • KTT Pattern (232 Total) • RTAX250S: 54 * 2 = 116 • RTAX1000S: 0 • RTAX2000S: 54 * 2 = 116 • Test protocol: • Two temperatures: -55 C (LTOL) and +125 C (HTOL) • Three increasing voltage steps: VCCA = {1.6, V2, V3} • 1000 hours at each voltage step • 500 hours HTOL • 500 hours LTOL Note: NASA programs focusing on RTAX250S and RTAX2000S models Notes: Nominal voltage = 1.5V Max voltage = 1.575V

10. Destructive Physical Analysis • Obtain samples of flight devices (2 each) • RTAX250S • RTAX1000S • RTAX2000S • Send to DPA Labs for analysis • Early samples in process Notes: 1. Above DPA’s to get “ahead of the curve.” 2. Actel cross sections two die per wafer as part of their QML process 3. NASA will DPA samples from each flight lot as part of incoming inspection

11. Radiation Testing • Complement the work of other groups (Actel, 561) • Total Ionizing Dose (TID) Testing • Low dose rate test • Parts in, preparing boards now • Single Event Effects (SEE) Testing • High fidelity test • PCB in design

12. Situational Awareness and Dissemination • Dissemination • NASA Advisories • http://klabs.org • quarterly briefings • OLD News • Monthly Design Seminars • Collecting Data or “Dots” • DPA Reports • Failure Analysis Reports • Application Lessons Learned • Dedicated RTAX-S Application Notes Page • Writing RTAX-S Application Notes (in progress) • http://klabs.org/richcontent/fpga_content/DesignNotes/rtax-s_ax/ • Similar to SX-S/SX-SU Page

13. Conclusions (1) • FPGA Reliability • Device • User Design and Application • Internal logic • Board level application • Electrical environment • Traditionally antifuse FPGAs have been highly reliable; RTSX-S (0.25 µm MEC, old programming algorithm) was problematic. • Traditionally user design and application has been highly problematic; this will not change no matter how much device level testing is done. • Goal: maximize flight reliability; device reliability is just one factor.

14. Conclusions (2) • Long Term Life Testing • Follow and trend commercial/industrial/military line and aerospace usage • RTAX-S parts should be used. • Larger difference between AX and RTAX-S then there was for A54SX-A and RTSX-SU. • 524 parts from this test are available if needed. • Lot splits: • Powered/unpowered • Low level radiation/normal environment • Phase 2 activity, if warranted. Base decision on results. • Real FPGA Problems To Solve (both general and RTAX-S Specific) • Unacceptable designs escape many reviews and are detected late • Expensive to fix • Launch slips • Fly unreliable designs • 1.5V power supply for core • Tight requirements, ± 75 mV • Single Event Transients are a serious issue • Same requirements for RTAX-S and Virtex II • Goal: maximize flight reliability; device reliability is just one factor.