Design and Implementation of VLSI Systems (EN0160)

1. Design and Implementation of VLSI Systems (EN0160) Lecture 34: Design Methods (beyond Tanner Tools) Prof. Sherief Reda Division of Engineering, Brown University Spring 2007 [sources: Weste/Addison Wesley – Maxfield/Newnes]

2. Stage I. IC Design, Verification, and Test Ideas Specification simulation/ verification Design C-based design (SystemC) schematics HDL (Verilog/VHDL) Test-structure Insertion library Synthesis gate-level design

3. FPGAs Floorplanning/placement Timing analysis routing Parasitic extraction download Power analysis Signal Integrity Stage II. IC Physical Implementation Flow Custom/Application Specific IC (ASIC) gate-level circuit Floorplanning/placement repeater insertion clock tree synthesis P/G network / routing metal fill insertion DRC/LVS mask generation / OPC reticles/masks

4. Stage III. Fabrication and Packaging reticles fabricate wafer Test dies dice and package the good ones chips

5. Stage I. IC Design, Verification, and Test Ideas Specification Design verification C-based design (SystemC) schematics HDL (Verilog/VHDL) Test-structure Insertion Library Synthesis gate-level design

6. Design Entry

7. Functional Simulation Make sure your design is logically correct.

8. Synthesis has to be “smart” Synthesis Synthesis transforms HDL to gates

9. We cannot try all possible input combinations to check our design How can we verify that our synthesizer is correct? Imagine you are designing a traffic light controller, how can you guarantee that the light will not be simultaneously green for both directions? Formal verification uses mathematical techniques to verify certain properties of your design. Verification

10. FPGAs Floorplanning/placement Timing analysis routing Parasitic extraction download Power analysis Signal Integrity Stage II. IC Physical Implementation Flow Custom/Application Specific IC (ASIC) gate-level circuit Floorplanning/placement repeater insertion clock tree synthesis P/G network / routing metal fill insertion DRC/LVS mask generation / OPC reticles/masks

11. Fast timing analysis using static timing analysis (STA) C17 from ISCAS’85 benchmarks I1 O1 I2 I3 I4 O2 I5 I6 • What is the worst delay of this circuit without regard to the dynamic input patterns? • What are the critical path(s) that lead to this delay?  perhaps timing can be improved if we adjust them

12. rows I/O pads [illegal placement] [legal placement] Placementof standard cells is a large-scale 2-D assignment problem  determines positions for thousands/millions of standard cells Floorplanning and placement Floorplanning(chip outlining) is a small scale 2-D assignment problem  determines positions for large blocks of logic/memory

13. data FF FF Minimum wirelength zero-skew tree for 64 FFs minimize demand on metal resources and reduces power extra delay clock minimize #buffers and maintain SI skew can lead to setup/hold times violations [Kahng et al., TCAS’92] Clock tree synthesis • Clock net(s)  delivers the periodic generated clock signal to FFs • Design objectives: • Zero-or prescribed skew • minimum wirelength • minimize buffers for signal integrity

14. What is the minimum number of repeaters to meet timing on this net? Repeater estimation for Itanium Repeater Stations Buffering (repeater insertion) for timing and signal integrity The situation is complicated in case of multi-pin nets: sink source sink

15. Design and analysis of power supply networks [Blaauw et al., DAC98] • Power supply network delivers Vdd/Gnd signals to all components. • Main challenges: • 1. IR drop: voltage at delivery point is degraded than the ideal voltage • performance drop • signal integrity problems • 2. electromigration PowerPC 750 power grid PowerPC 750 IR-drop map

16. Do you want this to happen to a net that belongs to the critical path?! Routing • Objective:determine routes (tracks, layers, and vias) for each net such that the total wirelength is minimized. • Be careful with routing critical nets and clock nets pin p1 congestion cell pin p2

17. create vias map to layers Routing and parasitic extraction • Multi-pin nets add more complexity in routing sink source sink • After all routes are determined, you can calculate the parasitic capacitance between each wire and its neighbors

18. Downforce Polishing pad Wafer carrier Slurry dispenser Wafer Polishing slurry Features Rotating platen Area fill features Post-CMP ILD thickness Fill insertion • CMP (chemical mechanical polishing) is executed for each layer before buildup of other layers • Remember the DRC violations from L-Edit! How can metal fill insertion helps in smoothing surfaces? [(animation is not technically correct!] [Photos are form Quirk/Serda]

19. MEBES fractured layout fractured layout into polygons (rectangles and trapezoids) [mask writer uses electron beam for printing patterns] Mask preparation and resolution enhancement techniques (RET) original layout GDSII

20. Mask preparation and resolution enhancement techniques (RET) Light source 193nm 130nm feature [Schellenberg, IEEE Spectrum’03]

21. Stage III. Fabrication and Packaging reticles fabricate wafer Test dies dice and package the good ones chips

22. Testing Functional (yield) How many circuits work (have no defects)? Delay/Power (parametric yield) What is the speed and power of the ones that work? Manufacturers speed bin their chips and sell them according to their performance percentage of chips 3.2Ghz 3.1Ghz 3.1Ghz 3.1Ghz 3.1Ghz 2.9Ghz 3.0Ghz F F 3.1Ghz 2.9Ghz Fabrication and Test

23. Dicing and packaging reticles dice wafer

24. Packaging choices

25. Overview of IC design flow We are done with main lectures We meet in exactly one week on May 4th to give your project presentations Summary